Ravi Monani Book a session Peer-reviewed research and industry technical papers spanning hardware security, low-power IC design, and validation.
IEEE ISVLSI 2025
A discrete-time Chua chaos-encryption core taken from model to synthesized RTL and 45nm physical design. The pipelined datapath reaches 100 kHz @ 0.9V at 0.486 uW and 0.005 mm^2 (76% utilization) - a lightweight on-chip secure-link primitive for constrained endpoints.
WISE 2024 - Workshop for Women in Hardware & Systems Security
Early prototype of a discrete-time Chua chaotic encryption pipeline, presenting a methodology that bridges algorithmic chaos modeling to a manufacturable low-power IC.
ISQED 2023 - International Symposium on Quality Electronic Design
Analyzes vulnerabilities in chaotic encryption for constrained IoT devices and proposes countermeasures against physical and encryption attacks using Chua's equation.
Discover Internet of Things (Springer)
A memristor-based Chua chaotic transceiver that improves both communication reliability and manufacturing security for constrained wearables and wireless sensors.
IEEE IGESSC 2022
A novel encryption architecture for low-power edge devices using chaotic equations, demonstrated through FPGA hardware co-simulation with efficient resource utilization.
California State University, Long Beach
Developed an encryption architecture using Time-Scaling Chaotic Shift Keying based on Chua's system, validated with comprehensive SPICE and FPGA simulations.
SVCC 2021 - Springer CCIS, vol. 1536
An in-depth examination of chaotic systems (Lorenz, Chua's, SprottD) for secure communication, analyzing power, area, and robustness as alternatives to software-based solutions.
California State University, Long Beach
Presented chaos-based CMOS encryption architecture on FPGA for secure communication.
University of New Mexico
Selected from 190 submissions to present chaos-based CMOS encryption research with LTspice simulation and FPGA implementation.
Springer CCIS
Presented 'Toward CMOS-Based Secure Communication with Low-Power Chaos Implementation.'
Internal technical conference
Presented an automation framework that reduces manual effort in microcode and firmware validation for CPU-core programs.
Internal technical conference
Presented a re-engineered validation pipeline that improves early defect interception and traceability for security-critical patches.
Internal technical conference
Presented an analytics approach for validation traceability and automated test-plan synthesis.
Internal technical conference
Presented a microcode-based methodology for deploying silicon workarounds without a firmware re-spin.
Internal technical conference
Presented a multi-tier framework for validating microcode against a range of processor security considerations.
Internal technical conference
Presented a machine-learning approach to clustering and triaging post-silicon validation failures.
Internal technical conference
Presented a remote validation methodology enabling multi-site collaboration on platform power and performance testing.